News from AMD’s Analyst Day
"Twice each year, AMD hosts an analyst day. The spring event, which took place at the Sunnyvale headquarters, is more technically oriented and tends to deal with the actual details of the company’s products and technology itself rather than financial performance and metrics. The event itself was relatively low key and included speakers from AMD and a few key partners, such as Sun, VMware, Rackable and video presentations from Microsoft and Alienware nee Dell. There was quite a bit of interesting information presented, but what really seemed to be worth dwelling on were the new revelations about the K8L and the 4x4 gaming systems.
Just as an aside, several architects at AMD expressed puzzlement at the origins of the K8L name. There is an internal engineering code name for the project, but the marketing team is slightly behind and has yet to provide something catchy for the rest of the world. At least one architect at AMD indicated a preference for the name K8++, but it seems unlikely that anyone in marketing or PR would share this point of view.
Do you Have Change for Some Cache?
Previously, Chuck Moore had described several incremental enhancements in the K8L at the Spring Processor Forum. The instruction fetch unit now includes an indirect branch predictor and fetches 32 bytes per cycle. The FP and SSE units have all been widened to 128 bits, as have the memory pipes. The load/store units also have somewhat more flexible execution; they can re-order loads with respect to other loads (although loads cannot move around stores). Physical and virtual addressing is expanded to 48 bits, and the page tables have been augmented as well. The page tables now support nesting for virtualization, and include 1GB pages. On the power side, the cores and system functionality will have separate power planes and independent C and P states. These are not all of the changes, but most of the key elements.
The first significant disclosures regarding the K8L had to do with the cache hierarchy within a single core. Despite an erroneous rumor to the contrary at Daily Tech, the L1D and L1I caches remain at 64KB each, according to a senior architect at AMD. The floor plan of the K8L also tends to confirm that the L1 caches have not decreased in size. The K8L did experience some L2 cache shrinkage and initial parts will feature a 2MB shared L3 cache. Based on the cache sizes, the L2 cache is still exclusive of the L1 contents, and the L3 cache is certainly not inclusive (although this does not mean it is exclusive). Additionally, it is easy to deduce, based on information about the load/store units that the bus between the L1 and L2 caches has been widened to 256 bits. The L3 cache is extensible, and it seems likely that 4MB parts will come out, perhaps as a way to differentiate between low-end parts intended for 1-2 sockets, and the higher-end parts for 4-8 sockets. "
Read entire story at: Real World Technology
AMD shows off details of K8L
the INQUIRER
"The one massive enhancement to the mix is that AMD finally has the ability to independently change core voltages for power savings. It now can also change the north bridge voltage independently of the cores. This is a huge win, we are told voltage differentials and problems with them were one of the main scaling headaches of the K8 core to this point.
Next is memory. The new core will support 48-bit addressing and 1GB pages. Cray and SGI will be very happy with this, until they hit that memory wall again. There is also official co-processor support, strongly hinted to be on a HTX card. The key here will be the platform is aware of them vs having to hack them in.
The other whopper Chuck dropped was that DDR2 is coming and DDR3 is in the wings when the spec 'settles down'. Old news, FB-DIMMs are the future, right? AMD has said they are supporting them, but the big news is that they are not forcing support. Unlike Intel's approach, Blackford supports only FBD, AMD will let you choose. This seems to strongly suggest that the controller on the later gens will be quite flexible indeed.
Next up is RAS, another area where AMD is sorely lacking. It is addressing the major sore points with support for memory mirroring, data poisoning support, and HT retry. It looks like it is following the IBM roadmap more than the Intel one here.
IPC is also going up in a big way. It is doing the obvious doubling of SSE/FP resources, old news now, but it goes a lot deeper than that. There are a bunch of added instructions, starting with the bit manipulation instructions LZCNT and POPCNT. It also added SSE extensions EXTRQ/INSERTQ and MOVNTSD/MOVNTSS. No word on SSE4 though.
The last bit is much more aggressive prefetch to 'feed the beast'. It has gone from 16B to 32B, an obvious step with the added SSE number crunching power. On top of this, it has out of order loads, and other tweaks to use the available bandwidth in a much more efficient manner.
For those who thought K8L was more or less a tweaked K8, you are wrong. It looks like no part of the core has been left unmolested by the elves working the CAD stations. It looks like AMD will have a credible response to the Intel MCW architecture after all. 2007 will be a fight after all. µ"
AMD's Next Generation Microarchitecture
Preview: from K8 to K8L
"July 27, 2006, Intel officially introduced its new Core 2 processor to the public. Based on the Conroe core, it proved to be a breakthrough in terms of CPU performance. AMD just doesn’t have a processor that could match the newest top-end models of the Core 2 series.
Unfortunately for AMD, the company was overconfident with its highly successful K8 series and didn’t prepare a timely response. According to the recently published roadmaps, AMD will release a new processor currently known under its codename of K8L (other sources refer to it as the K10) in the middle of the next year, i.e. a full year after Intel’s release of the Core 2.
The K8L is being originally designed as a quad-core chip. Its four execution cores will reside on a single silicon wafer and will all be connected to a shared L3 cache, to a common crossbar and to a common memory controller.
The already known and expected micro-architectural improvements in the upcoming processor will be discussed in this article. We will compare it with the Conroe micro-architecture to evaluate its possible fortes and weaknesses as well as future perspectives."
Read entire article at: X-bit labs